Hitachi HTS725050A9A364 Datasheet download pdf (Page 80)

7K500 OEM Specification

Page 80 of 176

Word Content

0 0002h Data Structure revision

1 Multiword DMA modes supported

15-3

Reserved

1 = Multiword DMA mode 2 and below are supported

1 = Multiword DMA mode 1 and below are supported

1 = Multiword DMA mode 0 is supported

2 Ultra DMA modes supported

15-6

Reserved

1 = Ultra DMA mode 5 and below are supported

1 = Ultra DMA mode 4 and below are supported

1 = Ultra DMA mode 3 and below are supported

1 = Ultra DMA mode 2 and below are supported

1 = Ultra DMA mode 1 and below are supported

1 = Ultra DMA mode 0 is supported

3-6 Maximum LBA address

7 Command set/feature set supported

15-9

Reserved

1 = 48-bit Addressing feature set supported

1 = Host Protected Area feature set supported

1 = Automatic acoustic management supported

Reserved

1 = Power-Up in Standby feature set supported

1 = Security feature set supported

1 = SMART error log supported

1 = SMART self-test supported

1 = SMART feature set supported

8 SATA feature

15-5

Reserved

1 = Software setting preservation supported

Reserved

1 = Interface power management supported

1 = Non-zero buffer offset in DMA Setup FIS supported

1 = Native command queuing supported

9-254 Reserved

255 Integrity word <Note .>

15-8 Checksum

7-0 Signature (A5h)

Table 46 Device Configuration Overlay Data structure

Note.

Bits 7:0 of this word contain the value A5h. Bits 15:8 of this word contain the data structure

checksum. The data structure checksum is the two’s complement of the sum of all byte in words 0

through 254 and the byte consisting of bits 7:0 of word 255. Each byte is added with unsigned

arithmetic, and overflow is ignored. The sum of all bytes is zero when the checksum is correct.

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Hitachi HTS725050A9A364 Datasheet Page 80

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